Carrier substrate

ABSTRACT

A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part application of and claims thepriority benefit of U.S. application Ser. No. 13/966,295, filed on Aug.14, 2013, now allowed, which claims the priority benefit of Taiwanapplication serial no. 102116226, filed on May 7, 2013. The entirety ofeach of the above-mentioned patent applications is hereby incorporatedby reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a substrate, and more particularly, to acarrier substrate suitable for carrying components.

2. Description of Related Art

In recent years, with the rapid progress of the electronic technology,high-tech electronic industries have appeared one after another, thusmore human-oriented, more performance-preferred electronic products arecontinuously evolving new things from the old, and have been designed tocater to the trend of being low-profiled and compact-sized. A carriersubstrate is usually disposed in the electronic products. The carriersubstrate, in addition to having conductive circuits, can also carrycomponents such as capacitors, inductors, resistors, IC chips, orpackage bodies to be used as data processing units of electronicproducts.

However, the connection pads and the traces on the known carriersubstrate are on the same horizontal plane, and the openings of thesolder mask layer expose the connection pads and the traces in thepre-connection region at the same time. Therefore, the arrangements notonly affect electrical performance by readily generating oxidationphenomenon to the traces, the user also cannot easily distinguish theconnection pads from the traces, and therefore the component cannot bedirectly connected with the connection pads accurately. Therefore,effectively allowing the user to directly connect the component to theconnection pads and preventing the traces from being exposed from theoutside of the solder mask layer are one of the goals industries todayare actively working toward.

SUMMARY OF THE INVENTION

The invention provides a carrier substrate which can allow the user toeasily distinguish connection pads for components and can prevent thegeneration of oxidation phenomenon from exposed traces.

The carrier substrate of the invention includes a dielectric layer, afirst circuit layer, an insulation layer, a plurality of conductiveblocks, and a first conductive structure. The dielectric layer has afirst surface and a second surface opposite to each other and aplurality of blind vias. The first circuit layer is embedded in thefirst surface of the dielectric layer and has an upper surface and alower surface opposite to each other. The upper surface is exposed fromthe first surface of the dielectric layer. The blind vias extend fromthe second surface to the first circuit layer and expose a portion ofthe lower surface of the first circuit layer. The insulation layer has athird surface and a fourth surface opposite to each other. Theinsulation layer is disposed on the first surface of the dielectriclayer through the fourth surface, and covers a portion of the uppersurface of the first circuit layer. The insulation layer has a pluralityof first openings extending from the third surface to the fourthsurface. The first openings expose another portion of the upper surfaceof the first circuit layer and the aperture of each first opening isincreased gradually from the third surface to the fourth surface.Moreover, the apertures of the first openings on the fourth surface aregreater than the width of the exposed first circuit layer. Theconductive blocks are respectively disposed in the first openings of theinsulation layer and connected with another portion of the upper surfaceof the first circuit layer exposed by the first openings. A top surfaceof each of the conductive blocks is higher than the third surface of theinsulation layer. The first conductive structure is disposed on thesecond surface of the dielectric layer and includes a plurality ofconductive vias filling the blind vias and a second circuit layerdisposed on a portion of the second surface.

In an embodiment of the invention, a height difference is between thetop surface of each of the conductive blocks and the third surface ofthe insulation layer, and the height difference is at least greater thanor equal to a thickness of the insulation layer.

In an embodiment of the invention, the carrier substrate furtherincludes a first surface treatment layer disposed on the top surface ofeach of the conductive blocks and extending along a side surface of eachof the conductive blocks on the third surface of the insulation layer.

In an embodiment of the invention, the side surface of each of theconductive blocks is an inclined surface.

In an embodiment of the invention, a material of the first surfacetreatment layer includes organic solderability preservative (OSP),electroplating Ni/Au, electroplating Ni/Pd, electroplating Sn,electroplating Ag, electroless Au, electroless nickel electrolesspalladium immersion gold (ENEPIG) or a combination thereof.

In an embodiment of the invention, the carrier substrate furtherincludes a solder mask layer disposed on another portion of the secondsurface of the dielectric layer and covering a portion of the secondcircuit layer of the first conductive structure, wherein the solder masklayer has a plurality of second openings exposing another portion of thesecond circuit layer.

In an embodiment of the invention, the carrier substrate furtherincludes a second surface treatment layer disposed on another portion ofthe second circuit layer.

In an embodiment of the invention, a material of the second surfacetreatment layer includes organic solderability preservative (OSP),electroplating Ni/Au, electroplating Ni/Pd, electroplating Sn,electroplating Ag, electroless Au, electroless nickel electrolesspalladium immersion gold (ENEPIG) or a combination thereof.

Based on the above, the first openings of the insulation layer of theinvention expose a portion of the first circuit layer and the conductiveblocks are disposed on the first circuit layer exposed by the firstopenings. As a result, the conductive blocks can be used as a structurefor elevating a portion of the first circuit layer. At the same time,the conductive blocks can be viewed as bonding pads for components. Inthis way, in subsequent applications of the carrier substrate of theinvention in carrying components (such as capacitors, inductors,resistors, IC chips, or package), the component can be accuratelyconnected with the conductive blocks to increase the reliability ofbonding between the carrier substrate and the component. Moreover, theinsulation layer covers another portion of the first circuit layer,which can protect the first circuit layer to prevent the generation ofoxidation phenomenon so as to maintain the electrical performance of thefirst circuit layer.

To make the above features and advantages of the invention morecomprehensible, several embodiments accompanied with drawings aredescribed in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A illustrates a cross-sectional schematic diagram of a carriersubstrate of an embodiment of the invention.

FIG. 1B illustrates a schematic top view of the circuit layer of FIG.1A.

FIG. 2A illustrates a cross-sectional schematic diagram of a carriersubstrate of another embodiment of the invention.

FIG. 2B illustrates a schematic top view of the circuit layer of FIG.2A.

FIG. 3A to FIG. 3F illustrate cross-sectional schematic diagrams of amanufacturing method of a carrier substrate of an embodiment of theinvention.

FIG. 3F′ illustrates a cross-sectional schematic diagram of a carriersubstrate of an embodiment of the invention.

FIG. 4 illustrates a cross-sectional schematic diagram of a carriersubstrate of an embodiment of the invention.

FIG. 4′ illustrates a cross-sectional schematic diagram of a carriersubstrate of another embodiment of the invention.

FIG. 4″ illustrates a cross-sectional schematic diagram of a carriersubstrate of yet another embodiment of the invention.

FIG. 5 illustrates a cross-sectional schematic diagram of a carriersubstrate of another embodiment of the invention.

FIG. 6 illustrates a cross-sectional schematic diagram of a carriersubstrate of another embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1A illustrates a cross-sectional schematic diagram of a carriersubstrate of an embodiment of the invention. FIG. 1B illustrates aschematic top view of the circuit layer of FIG. 1A. Referring first toFIG. 1A, in the present embodiment, a carrier substrate 100 a includes adielectric layer 110, a first circuit layer 120 a, an insulation layer130, a plurality of conductive blocks 140 a, and a first conductivestructure 150. Specifically, the dielectric layer 110 has two opposingsurfaces 112 and 114 and a plurality of blind vias 116 (FIG. 1Aschematically illustrates two). The first circuit layer 120 a isembedded in the surface 112 of the dielectric layer 110 and has twoopposing surfaces 121 a and 123 a, wherein the surface 121 a is exposedfrom the surface 112 of the dielectric layer 110. The blind vias 116extend from the surface 114 to the first circuit layer 120 a and exposea portion of the surface 123 a of the first circuit layer 120 a. Theinsulation layer 130 has two opposing surfaces 132 and 134, is disposedon the surface 112 of the dielectric layer 110 through the surface 134,and covers a portion of the surface 121 a of the first circuit layer 120a. The insulation layer 130 has a plurality of first openings 136extending from the surface 132 to the surface 134. The first openings136 expose another portion of the surface 121 a of the first circuitlayer 120 a, the aperture of each first opening 136 is increasedgradually from the surface 132 to the surface 134, and the apertures ofthe first openings 136 on the surface 134 are greater than the width ofthe exposed first circuit layer 120 a. The conductive blocks 140 a arerespectively disposed in the first openings 136 of the insulation layer130 and connected with another portion of the surface 121 a of the firstcircuit layer 120 a exposed by the first openings 136. The firstconductive structure 150 is disposed on the surface 114 of thedielectric layer 110. The conductive structure 150 includes conductivevias 150 a filling the blind vias 116 and a second circuit layer 150 bdisposed on a portion of the surface 114. Moreover, the carriersubstrate 100 a of the present embodiment can further include a soldermask layer 160, wherein the solder mask layer 160 is disposed on anotherportion of the surface 114 of the dielectric layer 110 and covers aportion of the second circuit layer 150 b of the first conductivestructure 150, wherein the solder mask layer 160 has a plurality ofsecond openings 162 exposing another portion of the second circuit layer150 b.

More specifically, referring to both FIG. 1A and FIG. 1B, the firstcircuit layer 120 a of the present embodiment includes a plurality oftraces 122 a and a plurality of connection pads 124 a, wherein the firstopenings 136 expose a portion of the connection pads 124 a. In otherwords, the traces 122 a are covered by the insulation layer 130, whichcan prevent generation of oxidation phenomenon due to the traces 122 abeing exposed from the outside, thus maintaining the electricalperformance of the traces 122 a. As shown in FIG. 1A, the surface 121 aof the first circuit layer 120 a of the present embodiment issubstantially exposed from the surface 112 of the dielectric layer 110and the conductive blocks 140 a fill the first openings 136 and directlyconnect with the connection pads 124 a structurally and electrically,wherein the first circuit layer 120 a and the conductive blocks 140 acan be an integral structure. In this way, the conductive blocks 140 acan be viewed as an elevating structure of the connection pads 124 a. Asa result, in subsequent applications of the carrier substrate 100 a ofthe present embodiment in carrying components (such as capacitors,inductors, resistors, IC chips, or package) (not illustrated), thecomponent can be accurately connected with the conductive blocks 136 toincrease the reliability of bonding between the carrier substrate 100 aand the component. Moreover, one surface 142 a of the conductive blocks140 a of the present embodiment is substantially lower than or levelwith (not illustrated) the surface 132 of the insulation layer 130 andthe sectional shape of the conductive blocks 140 a is, for instance, atrapezoid, but is not limited thereto.

It should be mentioned here that, the same reference numerals as theprevious embodiment and part of the contents thereof are used in thefollowing embodiments, wherein the same numerals are used to representthe same or similar components and descriptions of the same technicalcontents are omitted. The omitted portion is described in the previousembodiment and is not repeated in the following embodiments.

FIG. 2A illustrates a cross-sectional schematic diagram of a carriersubstrate of another embodiment of the invention. FIG. 2B illustrates aschematic top view of the circuit layer of FIG. 2A. Referring to bothFIG. 2A and FIG. 2B, the carrier substrate 100 b of the presentembodiment is similar to the carrier substrate 100 a of FIG. 1A, withthe difference being that the first circuit layer 120 b of the presentembodiment is only composed of a plurality of traces 122 b and a portionof the traces 122 b exposed by the first openings 136 can be used asconnection pads. Moreover, the surface 142 b of the conductive blocks140 b of the present embodiment is substantially level with or lowerthan (not illustrated) the surface 132 of the insulation layer 130.

In the following, an embodiment and FIG. 3A to FIG. 3F are used todescribe the manufacturing method of the carrier substrate 100 c indetail.

FIG. 3A to FIG. 3F illustrate cross-sectional schematic diagrams of amanufacturing method of a carrier substrate of an embodiment of theinvention. Referring first to FIG. 3A, according to the manufacturingmethod of the carrier substrate 100 a of the present embodiment, first,a first copper foil structure 20 a and a second copper foil structure 20b are laminated on two opposing surfaces 12 and 14 of a core dielectriclayer 10. Specifically, the first copper foil structure 20 a of thepresent embodiment includes a first thick copper foil layer 22 a, afirst thin copper foil layer 24 a, and a first release layer 26 a. Thefirst release layer 26 a is between the first thin copper foil layer 24a and the first thick copper foil layer 22 a. The second copper foilstructure 20 b includes a second thick copper foil layer 22 b, a secondthin copper foil layer 24 b, and a second release layer 26 b. The secondrelease layer 26 b is between the second thin copper foil layer 24 b andthe second thick copper foil layer 22 b. The first thick copper foillayer 22 a and the second thick copper foil layer 22 b are disposedcorrespondingly on the surfaces 12 and 14 of the core dielectric layer10.

Then, referring to FIG. 3B, two insulation layers 130 respectivelyhaving two opposing surfaces 132 and 134 are provided, and theinsulation layers 130 are respectively laminated on the first copperfoil structure 20 a and the second copper foil structure 20 b by thesurfaces 132, wherein the insulation layers 130 have a plurality offirst openings 136 extending from the surfaces 134 to the surfaces 132.In particular, the apertures of the first openings 136 are increasedgradually from the surfaces 132 to the surfaces 134. Here, the materialof the insulation layers 130 is, for instance, ABF (Ajinomoto build-upfilm) resin, and the insulation layers 130 are stacked on the firstcopper foil structure 20 a and the second copper foil structure 20 bthrough a method of thermocompression bonding. Moreover, the firstopenings 136 are, for instance, formed by laser drilling.

Then, referring to FIG. 3C, a first circuit layer 120 c is respectivelyformed on a portion of the surfaces 134 of the insulation layers 130 anda plurality of conductive blocks 140 c fill the first openings 136.Specifically, in the present embodiment, the step of forming the firstcircuit layers 120 c and the conductive blocks 140 c includescomprehensively forming a seed layer (not illustrated) on the surfaces134 of the insulation layers 130 and the surfaces of the first openings136 and forming a patterned dry film M on the surfaces 134 of theinsulation layers 130, wherein the patterned dry film M exposes aportion of the surfaces 134 of the insulation layers 130. Then, anelectroplating process is performed to form the first circuit layers 120c on the surfaces 134 of the insulation layers 130 exposed by thepatterned dry film M and the conductive blocks 140 c filling the firstopenings 136. Then, the patterned dry film M is removed. In short, thecircuit layers 120 c and the conductive blocks 140 c are integrallyformed.

It should be mentioned that, in the present embodiment, the circuitlayers 120 c can also be composed of only a plurality of traces orcomposed of a plurality of traces and a plurality of connection pads,wherein the first openings 136 can expose a portion of the traces to beused as connection pads or directly expose a portion of the connectionpads. In other words, the traces not used as connection pads are coveredby the insulation layers 130, which can prevent the generation ofoxidation phenomenon due to the traces being exposed from the outside,thus maintaining the electrical performance of the traces. Moreover, thetraces or connection pads exposed by the first openings 136 can bedirectly connected with the conductive blocks 140 c structurally andelectrically.

Then, referring to FIG. 3D, a dielectric layer 110 is respectivelylaminated on another portion of the surfaces 134 of the insulationlayers 130 and the first circuit layers 120 c, wherein the dielectriclayers 110 have a plurality of blind vias 116 extending to a portion ofthe first circuit layers 120 c. Then, referring further to FIG. 3D, afirst conductive structure 150 is respectively formed on the dielectriclayers 110, wherein the first conductive structures 150 include aplurality of conductive vias 150 a filling the blind vias 116 and aplurality of second circuit layers 150 b disposed on a portion of thedielectric layers 110.

Then, referring to FIG. 3E, a solder mask layer 160 is respectivelyformed on another portion of the dielectric layers 110 and cover aportion of the first conductive structures 150, wherein the solder masklayers 160 have a plurality of second openings 162 exposing anotherportion of the first conductive structure 150.

Lastly, referring to both FIG. 3E and FIG. 3F, the first copper foilstructure 20 a, the second copper foil structure 20 b, and the coredielectric layer 10 are removed to expose the surfaces 132 of theinsulation layers 130 and the conductive blocks 140 c. Specifically, thefirst thin copper foil layer 24 a and the second thin copper foil layer24 b are separated from the core dielectric layer 10, the first thickcopper foil layer 22 a, and the second thick copper foil layer 22 b bypeeling the first release layer 26 a and the second release layer 26 b.Then, an etching process is performed to etch the first thin copper foillayer 24 a and the second thin copper foil layer 24 b to expose thesurfaces 132 of the insulation layers 130 and the conductive blocks 140c. It should be mentioned that, due to the adjustments of the etchingprocess, the surfaces 142 c of the conductive blocks 140 c can be lowerthan or level with (not illustrated) the surfaces 132 of the insulationlayers 130. At this point, the manufacture of the carrier substrate 100c is complete.

It should be mentioned that, the invention does not limit the number ofthe dielectric layer 110 and the conductive circuit layers (such as thesecond circuit layer 150 b and the first circuit layer 120 c). Althoughthe dielectric layer 110 mentioned in FIG. 3F substantially only has onelayer, however, the conductive circuit layer substantially has twolayers (the first circuit layer 120 c and the second circuit layer 150).However, in other unillustrated embodiments, after the step of FIG. 3D,that is, after forming the second circuit layers 150 on the dielectriclayers 110, the steps of FIG. 3C to FIG. 3D can also be repeated once ora plurality of times to form a built-up structure, which still belongsto the usable technical solution of the invention and does not departfrom the scope of the invention to be protected.

For instance, referring to FIG. 3F′, the carrier substrate 100 d of thepresent embodiment can further include a built-up structure 150′.Specifically, the built-up structure 150′ is disposed on the surface 114of the second circuit layer 150 b and the dielectric layer 110. Thebuilt-up structure 150′ includes at least one built-up dielectric layer152 and a second conductive structure 154 disposed on the built-updielectric layer 152, wherein the second conductive structure 154 atleast includes a plurality of second conductive vias 154 a disposed inthe built-up dielectric layer 152 and a built-up circuit layer 154 bdisposed on a portion of the built-up dielectric layer 152, and aportion of the second conductive vias 154 a connect with the secondcircuit layer 150 b. The solder mask layer 160 is disposed on anotherportion of the outermost built-up dielectric layer 152 of the built-upstructure 150′ and covers a portion of the outermost second conductivestructure 154, wherein the solder mask layer 160 has a plurality ofsecond openings 162 exposing another portion of the second conductivestructure 154.

In short, the carrier substrate 100 d of the present embodiment has twodielectric layers (dielectric layer 110 and built-up dielectric layer152) and three conductive circuit layers (first circuit layer 120 c,second circuit layer 150 b, and built-up circuit layer 154 b). Here, theconductive blocks 140 c filling the first openings 136 of the insulationlayer 130 are suitable for electrically connecting, for instance, with achip having smaller electrical linewidth/line distance (notillustrated), wherein conductive bumps (not illustrated) for connectionare arranged on the chip. The built-up circuit layer 154 b of the secondconductive structure 154 exposed by the second openings 162 of thesolder mask layer 160 can be viewed as a connection pad suitable forelectrically connecting, for instance, with a printed circuit boardhaving greater electrical spacing. In this way, the carrier substrate100 d of the present embodiment is suitable for carrying components ofdifferent electrical spacings.

In other embodiments, referring to FIG. 4, after the step of FIG. 3F,that is, after removing the first copper foil structure 20 a, the secondcopper foil structure 20 b, and the core dielectric layer 10, aplurality of solder balls 170 can be respectively formed on theconductive blocks 140 c, wherein the solder balls 170 respectivelyconnect with the conductive blocks 140 c to complete the manufacture ofthe carrier substrate 100 e.

Alternately, referring to FIG. 4′, after the step of FIG. 3F, that is,after removing the first copper foil structure 20 a, the second copperfoil structure 20 b, and the core dielectric layer 10, a plurality ofconductive bumps 180 can be respectively formed on the conductive blocks140 c, wherein the conductive bumps 180 respectively connect with theconductive blocks 140 c and cover a portion of the insulation layer 130to complete the manufacture of the carrier substrate 100 f.

Alternately, referring to FIG. 4″, after the step of FIG. 3F, that is,after removing the first copper foil structure 20 a, the second copperfoil structure 20 b, and the core dielectric layer 10, a plurality ofconductive towers 190 can be respectively formed on the conductiveblocks 140 c, wherein each conductive tower 190 has a tip face 192 and abase face 194 opposite to each other and the diameter of each conductivetower 190 is increased gradually from the tip face 192 to the base face194. Then, a plurality of solder bumps 195 is respectively formed tocover the conductive towers 190 to complete the manufacture of thecarrier substrate 100 g.

FIG. 5 illustrates a cross-sectional schematic diagram of a carriersubstrate of another embodiment of the invention. Referring to FIG. 5,the carrier substrate 100 h of the present embodiment is similar to thecarrier substrate 100 a of FIG. 1A and carrier substrate 100 b of FIG.2A, with the difference being that a top surface 142 d of each of theconductive blocks 140 d of the present embodiment is substantiallyhigher than the surface 132 d of the insulation layer 130 d. In moredetail, a height difference H is between the top surface 142 d of eachof the conductive blocks 140 d and the surface 132 d of the insulationlayer 130 d. Herein, the height difference H is at least greater than orequal to a thickness T of the insulation layer 130. In other words, eachof the conductive blocks 140 d is at least twice the thicker than theinsulation layer 130, and the top surface 142 d of each of theconductive blocks 140 d protrudes out of the surface 132 d of theinsulation layer 130 d.

As shown in FIG.5, since the aperture of each first opening 136 isincreased gradually from the surface 132 d to the surface 134 d, so aside surface 144 d of each of the conductive blocks 140 d is not asurface perpendicular to the surface 132 d of the insulation layer 130d. Specifically, the side surface 144 d of each of the conductive blocks140 d is inclined relative to the surface 132 d of the insulation layer130 d. In other words, the side surface 144 d of each of the conductiveblocks 140 d is an inclined surface. Furthermore, in terms ofmanufacturing processes, the height difference H may be formed byreducing the thickness of the insulation layer 130 described in FIG. 1and FIG. 2, and a method of the reducing the thickness of the insulationlayer 130 is a physical or chemical process. It should be mentioned herethat, the first circuit layer 120 d of the present embodiment, forexample, can include a plurality of traces and a plurality of connectionpads or only composed of a plurality of traces, but the disclosure isnot limited thereto.

Briefly, the conductive blocks 140 d are disposed on the first circuitlayer 120 d exposed by the first openings 136, and the top surface 142 dof each of the conductive blocks 140 d is substantially higher than thesurface 132 d of the insulation layer 130 d. As a result, the conductiveblocks 140 d can be used as a structure for elevating a portion of thefirst circuit layer 120 d. At the same time, the conductive blocks 140 dcan be viewed as bonding pads for components. In this way, in subsequentapplications of the carrier substrate 100 h of the embodiment incarrying components (such as capacitors, inductors, resistors, IC chips,or package), the component can be accurately connected with theconductive blocks 140 d to increase the reliability of bonding betweenthe carrier substrate 100 h and the component.

FIG. 6 illustrates a cross-sectional schematic diagram of a carriersubstrate of another embodiment of the invention. Referring to FIG. 6,the carrier substrate 100 i of the present embodiment is similar to thecarrier substrate 100 h of FIG.5, with the difference being that thecarrier substrate 100 i further includes a first surface treatment layerS1 and a second surface treatment layer S2. In more detail, the firstsurface treatment layer S1 is disposed on the top surface 142 d of eachof the conductive blocks 140 d and extends along the side surface 144 dof each of the conductive blocks 140 d on the surface 132 d of theinsulation layer 130 d, so as to prevent the conductive blocks 140 dbeing oxidized or polluted by external substances. Herein, a material ofthe first surface treatment layer S1 is organic solderabilitypreservative (OSP), electroplating Ni/Au, electroplating Ni/Pd,electroplating Sn, electroplating Ag, electroless Au, electroless nickelelectroless palladium immersion gold (ENEPIG) or a combination thereof.The second surface treatment layer S2 is disposed on another portion ofthe second circuit layer 150 b, so as to prevent the second circuitlayer 150 b being oxidized or polluted by external substances. Herein, amaterial of the second surface treatment layer S2 is the same as amaterial of the first surface treatment layer S1, such as organicsolderability preservative (OSP), electroplating Ni/Au, electroplatingNi/Pd, electroplating Sn, electroplating Ag, electroless Au, electrolessnickel electroless palladium immersion gold (ENEPIG) or a combinationthereof.

Based on the above, the first openings of the insulation layer of theinvention expose a portion of the first circuit layer and the conductiveblocks are disposed on the first circuit layer exposed by the firstopenings. As a result, the conductive blocks can be used as a structurefor elevating a portion of the first circuit layer. At the same time,the conductive blocks can be viewed as bonding pads for components. Inthis way, in subsequent applications of the carrier substrate of theinvention in carrying components (such as capacitors, inductors,resistors, IC chips, or package), the component can be accuratelyconnected with the conductive blocks to increase the reliability ofbonding between the carrier substrate and the component. Moreover, theinsulation layer covers another portion of the first circuit layer,which can protect the first circuit layer to prevent the generation ofoxidation phenomenon so as to maintain the electrical performance of thefirst circuit layer.

Although the invention has been described with reference to the aboveembodiments, it will be apparent to one of the ordinary skill in the artthat modifications to the described embodiments may be made withoutdeparting from the spirit of the invention. Accordingly, the scope ofthe invention is defined by the attached claims not by the abovedetailed descriptions.

What is claimed is:
 1. A carrier substrate, comprising: a dielectriclayer having a first surface and a second surface opposite to each otherand a plurality of blind vias; a first circuit layer embedded in thefirst surface of the dielectric layer and having an upper surface and alower surface opposite to each other, the upper surface exposed from thefirst surface of the dielectric layer, wherein the blind vias extendfrom the second surface to the first circuit layer and expose a portionof the lower surface of the first circuit layer; an insulation layerhaving a third surface and a fourth surface opposite to each other anddisposed on the first surface of the dielectric layer through the fourthsurface and covers a portion of the upper surface of the first circuitlayer, the insulation layer having a plurality of first openingsextending from the third surface to the fourth surface, wherein thefirst openings expose another portion of the upper surface of the firstcircuit layer, an aperture of each first opening is increased graduallyfrom the third surface to the fourth surface, and the apertures of thefirst openings on the fourth surface are greater than a width of theexposed first circuit layer; a plurality of conductive blocksrespectively disposed in the first openings of the insulation layer andconnected with another portion of the upper surface of the first circuitlayer exposed by the first openings, wherein a top surface of each ofthe conductive blocks is higher than the third surface of the insulationlayer; and a first conductive structure disposed on the second surfaceof the dielectric layer and comprising a plurality of conductive viasfilling the blind vias and a second circuit layer disposed on a portionof the second surface.
 2. The carrier substrate as recited in claim 1,wherein a height difference is between the top surface of each of theconductive blocks and the third surface of the insulation layer, and theheight difference is at least greater than or equal to a thickness ofthe insulation layer.
 3. The carrier substrate as recited in claim 1,further comprising: a first surface treatment layer disposed on the topsurface of each of the conductive blocks and extending along a sidesurface of each of the conductive blocks on the third surface of theinsulation layer.
 4. The carrier substrate as recited in claim 3,wherein the side surface of each of the conductive blocks is an inclinedsurface.
 5. The carrier substrate as recited in claim 3, wherein amaterial of the first surface treatment layer comprising organicsolderability preservative (OSP), electroplating Ni/Au, electroplatingNi/Pd, electroplating Sn, electroplating Ag, electroless Au, electrolessnickel electroless palladium immersion gold (ENEPIG) or a combinationthereof.
 6. The carrier substrate as recited in claim 1, furthercomprising: a solder mask layer disposed on another portion of thesecond surface of the dielectric layer and covering a portion of thesecond circuit layer of the first conductive structure, wherein thesolder mask layer has a plurality of second openings exposing anotherportion of the second circuit layer.
 7. The carrier substrate as recitedin claim 6, further comprising: a second surface treatment layerdisposed on the another portion of the second circuit layer.
 8. Thecarrier substrate as recited in claim 6, wherein a material of thesecond surface treatment layer comprising organic solderabilitypreservative (OSP), electroplating Ni/Au, electroplating Ni/Pd,electroplating Sn, electroplating Ag, electroless Au, electroless nickelelectroless palladium immersion gold (ENEPIG) or a combination thereof.